A dual-ported RAM for the MC6847

My CZ80 computer design requires a dual-ported RAM between the Z80 and the MC6847, to solve the memory contention problem. Now that the RAMs have arrived, I modified the MC6847 test circuit to try them out.

48-pins IDT7132 / IDT7130 RAMs, and an AT28C64B EEPROM for size comparison

The MC6847 was set to text mode. I removed the EEPROM from the circuit and replaced it with the 2KB IDT7132 RAM. The MC6847 will be reading data from the RAM, which is obviously full of random bytes. To make thinks more predictable, this is how I wired the dual-ported RAM.

For the left port:

  • Data bus is wired to the MC6847 data bus;
  • Address bus A0-A8 is wired to the MC6847 address bus;]
  • CE is tied low (always active);
  • R/W is tied high (read mode);
  • OE is tied low (output always enabled).

For the right port:

  • Data bus is wired to VCC or GND to form the pattern 0x41 (character “A”);
  • Address bus A0-A8 is also wired to the MC6847 address bus, but with A8 inverted by a 74LS04;
  • CE is tied low (always active);
  • R/W is tied low (write mode, so OE is ignored).

This configuration is essentially a stress test for the dual-port RAM: one side is constantly being written to, and the other side is constantly being read from. The reason to invert one of the address lines is to avoid collisions: the dual-ported RAM can handle concurrent access to its memory cells, but if the same address is both read from and written to at the exact same time, it will flag a BUSY state to one of the sides. Since there is no CPU in this circuit, handling the BUSY signal would be difficult. With the inverted A8 line, one half of the screen is written to while the other half is read from, so there will never be a collision.

This is the new circuit board:


The MC6847 is on the upper left. The IDT7132 RAM on upper middle (with right side port facing up), and the 74LS04 inverter on the upper right. The bottom half of the board is the same (clock, color mixer and amplifier), except that I changed some resistor chains to a single resistor of the correct value. The resulting picture:


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